Damascene interconnection and semiconductor device

ABSTRACT

A semiconductor device includes an insulating film. On this insulating film, are formed an interconnection trench communicating with a semiconductor element and a pad trench communicating with the interconnection trench. In the pad trench, a protrusion is formed by leaving one part of the insulating film. A conductive film is formed over the insulating film including the interconnection and pad trenches. Thereafter, the conductive film is removed by a CMP process. At this time, the protrusion serves to prevent the conductive film in the pad trench from being over-polished.

TECHNICAL FIELD

This invention relates to damascene interconnections and semiconductordevices. More particularly, the invention relates to a damasceneinterconnection having a bonding pad formed by a pad trench and a metalor conductive film filling the pad trench, and to a semiconductor deviceusing same.

PRIOR ART

Recently, so-called the damascene process has being adopted in providingmultilevel interconnections for a semiconductor device having a metal orconductive film buried in the insulating film.

Briefly explaining a general damascene interconnection, an insulatingfilm 2 formed on a semiconductor substrate 1 as shown in FIG. 1(a) isetched using a mask of resist 3 patterned corresponding to aninterconnection, as shown in FIG. 1(b), thereby forming a trench 4.After removing away the resist 3, a conductive film 5 is formed coveringthe trench 4 as shown in FIG. 1(c). Then, the conductive film 5 in areasother than the trench 4 is removed in a polishing process using, forexample, a Chemical Mechanical Polish process (hereinafter referred toas “CMP process”), as shown in FIG. 1(d).

It is known that, where the conductive film 5 is removed by the CMPprocess, as the opening area of the trench increases, the polish rate onthe conductive film buried in the trench increases, as shown in FIG. 2.In regions having a small trench opening area, such as is customary ininterconnections, there are no particular problems. However, in regionshaving a large trench opening area, such as a bonding pad 6 shown inFIG. 3, the conductive film 5 in the trench is polished into a dish-likeform by an abrasive as shown in FIG. 4, thus resulting in so-calleddishing. Due to this, there are cases a disconnect or an increase ofresistance occurs in a central portion A where the wall thickness isreduced when providing connection between the bonding pad and the ICframe.

SUMMARY OF THE INVENTION

Therefore, it is a primary object of the present invention to provide anovel damascene interconnection and semiconductor device.

Another object of the invention is to provide a damasceneinterconnection capable of preventing increases in resistance value ordisconnects caused by dishing in a bonding pad, and a semiconductordevice using the same.

A damascene interconnection according to the present invention,comprises: an interconnection trench formed in an insulating film and apad trench communicating therewith; a protrusion formed by a portion notremoved of the insulating film in the pad trench to decrease asubstantial opening area of the pad trench; and a conductive film buriedin the interconnection trench and the pad trench.

In the case of using such a damascene interconnection for asemiconductor device, such a semiconductor device, comprises: asemiconductor substrate; an insulating film formed on the semiconductorsubstrate; an interconnection trench formed on the insulating film andcommunicating with a semiconductor element; a pad trench formed on theinsulating film and communicating with the interconnection trench; aprotrusion formed by a portion of not removed of the insulating film inthe pad trench and reducing a substantial opening area of the padtrench; and a conductive film buried in the interconnection trench andthe pad trench.

When removing the conductive film by a CMP process or the like, theprotrusion dividing the pad trench serves as a stop for polishing by anabrasive. Consequently, so-called dishing will not occur such that theconductive film in the pad trench is excessively removed. Thus,according to the invention, it is possible to prevent increases inresistance or disconnects resulting from dishing on a bonding pad.

The protrusion may be formed not to divide the conductive film buried inthe pad trench, or formed to divide the conductive film. However, wherethe conductive film is divided, another means is required toelectrically couple together divided conductive film portions. The othermeans may be a contact hole for connecting between the conductive filmformed in the insulating film and a conductive film arranged in a levellower than the insulating film. It should be noted that the contact holeis effective also where the conductive film in the pad trench is notdivided by a protrusion.

The protrusion includes, in one embodiment, island protrusionsdistributed in a proper interval in the pad trench, and in anotherembodiment ridges.

The above described objects and other objects, features, aspects andadvantages of the present invention will become more apparent from thefollowing detailed description of the present invention when taken inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustrative view showing a process for a general damasceneinterconnection;

FIG. 2 is a graph showing a usual polish characteristic in CMP;

FIG. 3 is an illustrative view showing a prior art bonding pad;

FIG. 4 is a sectional view taken along line X—X in FIG. 3;

FIG. 5 is an illustrative view showing one embodiment of the presentinvention;

FIG. 6 is a sectional view taken along line VI—VI in FIG. 5;

FIG. 7 is an illustrative view showing a method for forming the FIG. 5embodiment;

FIG. 8 is an illustrative view showing another embodiment of theinvention;

FIG. 9 is an illustrative view showing another embodiment of theinvention;

FIG. 10 is an illustrative view showing another embodiment of theinvention;

FIG. 11 is a sectional view on line XI—XI in FIG. 10;

FIG. 12 is an illustrative view showing another embodiment of theinvention; and

FIG. 13 is an illustrative view showing another embodiment of theinvention.

BEST FORM FOR PRACTICING THE INVENTION

A semiconductor device 10 of the embodiment shown in FIG. 5 and FIG. 6includes a semiconductor substrate 12 formed, for example, of silicon(Si) or the like. Note that the semiconductor substrate 12 may be othermaterials. Semiconductor elements, including active and/or passiveelements, are formed on the semiconductor substrate 12, although theyare not shown in the figure.

The semiconductor device 10 comprises a damascene interconnection 11including, on the semiconductor substrate 12, an interconnection trench16 extending from the semiconductor element (not shown) and a pad trench18 connected to the interconnection trench 16. That is, an insulatingfilm 14 is formed, for example, of silicon oxide (SiO₂) in a uniformfilm thickness on the semiconductor substrate. In the insulating film14, the interconnection trench 16 and the pad trench 18 connectedtherewith are formed. The insulating film 14 may be other materials.

Note that FIG. 5 and FIG. 6 illustrate the insulating film 14 formeddirectly on the surface of the semiconductor substrate 12 in order tosimplify illustration and explanation. However, in the actualsemiconductor device, one or a plurality of semiconductor element layersare formed on the semiconductor substrate 12, as is well known in theart, and an interconnection layer is formed as required on each of suchsemiconductor element layers. The interconnection trench 16 provideselectrical connection between the semiconductor element (not shown) andthe pad trench 18. The pad trench 18 serves as a bonding pad on whichwire-bonding is to be made to a not-shown IC leadframe. That is, the padtrench 18 is a connection terminal to provide electric conduction of thesemiconductor element on each layer to and from the IC leadframe.

It has been a conventional practice to form such a damasceneinterconnection 11 by merely filling a conductive film, such as ofcopper (Cu), aluminum (Al) or tungsten (W), in the interconnectiontrench 16 and pad trench 18.

In this embodiment, however, the following devise is implemented on thepad trench 18 with a comparatively large opening area, in order toprevent dishing as stated before. That is, the pad trench 18 has aninsulating film 14 formed to be left as an island-spotted form.Consequently, the pad trench 18 is divided into unitary portions byisland protrusions 20. However, the island protrusions 20 do notseparate one portion from another portion of the pad trench 18, i.e. thepad trench 18 is continuous in areas except for the island protrusions20. That is, the pad trench 18 in this embodiment has a large openingsize but is reduced in its substantial opening area by the presence ofthe island protrusions 20. Specifically, in this embodiment the padtrench 18 has a side determined as approximately 50-200 μm and aninterval of the protrusions 20 determined as approximately 5-20 μm.

In the pad trench 18 thus having the island-spotted protrusions 20, aconductive film 22 is formed using a metal as mentioned before orconductive material in a manner similar to that of the interconnectiontrench 16. Thus, the semiconductor element (not shown) on thesemiconductor device 10 is electrically coupled through the conductivefilm 22 buried in the interconnection trench 16 to the pad trench 18,i.e. the conductive film 22 buried in the pad trench 18. Due to this, bybonding a wire (not shown) to the conductive film 22 formed in the padtrench 18, the semiconductor element is put in electrical connection tothe wire, i.e. to the IC leadframe.

Hereunder, explanation is made on a method to concretely manufacture asemiconductor device 10 of the embodiment having a damasceneinterconnection 11 as described above, with reference to FIG. 7.Incidentally, in FIG. 7, an insulating film 14 is formed directly on asurface of a semiconductor substrate 12. It should however be noted thatthe semiconductor device 10, in practice, has a proper number ofsemiconductor element layers as stated before and FIG. 7 depicts aninterconnection structure having only one layer for the sake ofconvenience.

An insulating layer 14 is formed on a semiconductor substrate 12 bythermal oxidation process or the like, as shown in FIG. 7(a).Thereafter, the insulating film 14 is masked with patterned resist 24 toleave island protrusions 20. Etching is made to form an interconnectiontrench 16 and a pad trench 18. At this time, a plurality of islandprotrusions 20 are formed in the pad trench 18. After removing theresist 24, a conductive film 22 is formed over an entire surface of thesemiconductor substrate 12 including the interconnection trench 16 andpad trench 18 by a CVD or hot sputter process, as shown in FIG. 7(c).Then, the conductive film 22 on the insulating film 14 is removed asshown in FIG. 7(d) by a CMP process.

In the CMP process, the semiconductor substrate 12 (including theinsulating film 14 and the conductive film 22) is urged onto a polishingpad mounted on a polisher table. The table and the substrate holder arerelatively rotated while supplying to the polishing pad a slurrycontaining abrasive particles. When the conductive film 22 on theinsulating film 14 is removed, the polishing operation is finished. Inthis case, the abrasive particle for polishing is selected of a kind(material, particle size, etc.) such that in CMP a polish rate on theinsulating film 14 is lower than a polish rate on the conductive film22. According to an experiment conducted by the present inventors, thepolish rate in concrete is desirably given as (polish rate on theconductive film 22)/(polish rate on the insulating film 14)≧20 to 10.This is because in CMP the conductive film 22 on the insulating film 14needs to be removed as rapidly as possible. However, the insulating film14 should be prevented from being damaged due to polishing, and theisland projections 20 are to prevent over-polishing the conductive film22 of the pad trench 18. Consequently, there is a necessity of providingthe insulating film 14 with greater polish resistance than that of theconductive film 22.

According to this embodiment, in the process of removing the conductivefilm 22 (FIG. 7(d)), the protrusions 20 (insulating film 14) having alow polish rate act such that the conductive film 22 is deceleratedduring the process of polishing by the polish pad. Thus, the conductivefilm 22 in the pad trench 18 can be prevented from being removed to anexcessive extent. This in turn makes it possible to prevent the padtrench 18 from increasing in resistance or the occurrence of disconnectsdue to dishing.

That is, in the conventional art shown in FIG. 3 and FIG. 4, because thepad trench 6 is contacted in its entire opening by a polish pad (notshown), the pad trench 6 having a large opening area is partlyover-polished resulting in dishing. On the contrary, in this embodiment,despite the pad trench is large in an opening area, the opening isdivided into unitary portions wherein the opening area is small ifconsidered on a portion sandwiched between the island protrusions 20.Due to this, over-polish will not occur. As a result, a conductive film22 in the pad trench 18 is given a planar surface as shown in FIG. 6 andFIG. 7(d).

In this manner, in the present invention, where using a CMP methodhaving a polish characteristic that the polish rate increases with anincrease in the opening area, the forming of protrusions in the padtrench reduces the substantial opening area, thereby preventing dishing.

Incidentally, the protrusions 20 may be in a form to divide the padtrench 18 into portions. The shape of a protrusion may be a straightline as shown in FIG. 8 or a squared-spiral form as shown in FIG. 9.

That is, in the embodiment shown in FIG. 8, a plurality of protrusionsor ridges 20 are formed extending from respective outer edges of foursides of a rectangular pad trench 18. It should be noted that, in alsothis case, the other areas of the pad trench 18 are continuous with oneanother. In also this embodiment, the substantial opening area isreduced in the areas between the protruding ridges 20, betweenprotruding ridges extending from different sides, and between theprotruding ridge 20 and the inner edge of the pad trench 18.

In the embodiment of FIG. 9, a pad trench 18 has one ridge 20 formed ina squared-spiral form. In the FIG. 9 embodiment, because the ridge 20 isin the spiral form, the pad trench 18 is not divided into non-continuousareas. In this manner, by forming the ridge 20 in the spiral form, theopening area is substantially reduced in the areas between portions ofthe ridge 20 and between the ridge 20 and the pad trench 18 inner edge.

Meanwhile, if necessary, connection holes or contact holes 26 may beformed through a bottom of the pad trench 18 to provide electricalconnection between the conductive film 22 and a not-shown lower-levelconductive film through these contact holes 26.

Explanation is made in detail on an embodiment having contact holes 26formed through the insulating film 14, with reference to FIG. 10 andFIG. 11. This embodiment is to be applied to a semiconductor devicehaving another layer formed in a level lower than the insulating film14, as shown in FIG. 11. That is, another insulating film 28 is formedon a semiconductor substrate 12, and further another conductive film 30is formed on the insulating film 28. The insulating film 14 is formed onthe conductive film 30. In a bottom of the pad trench 18, a plurality ofcontact holes 26 are formed penetrating through the insulating film 14.When forming a metal or conductive film 22 in the pad trench 18, a metalor conductive material thereof is also filled in the contact holes 26 toprovide electrical connection between the upper-leveled conductive film22 and lower-leveled conductive film 30. By thus forming the contactholes 26 in the pad trench 18 and connecting the conductive films 22 and30, it is possible to eliminate the disadvantage as feared upon formingprotrusions 20 in the pad trench 18.

That is, the protrusions or ridges, if formed in the pad trench 18,result in a volume decrease of the pad trench 18, i.e. volume reductionof the conductive film 22 of the pad trench 18. It is to be feared thatthe bonding pad may be increased in electric resistance by the volumereduction in the conductive film 22 of the pad trench 18. However, theconductive film 22, if coupled to the conductive film 30 as in the FIG.10 and FIG. 11 embodiments, increases the effective volume of theconductive film 22, thus properly suppressing the electric resistancefrom increasing.

In an embodiment shown in FIG. 12, contact holes 26 are added to thestructure of the FIG. 8 embodiment to thereby make the conductive film22 of the pad trench 18 integral with a lower-leveled conductive film.

In an embodiment of FIG. 13, a ridge 20 is formed in a closed-loop formin a manner different from the FIG. 9 embodiment. Accordingly, in thisembodiment the conductive film 22 of the pad trench 18 is divided intoportions, in a manner different from the above embodiment. In this case,the contact holes 26 are especially effective. That is, the formation ofcontact holes 26 connects the conductive film 22 of the pad trench 18 toa lower-leveled conductive film 30 (FIG. 11). Consequently, the dividedportions of the conductive film 22 of the pad trench 18 are electricallycoupled together through the conductive film 30. That is, in the FIG. 13embodiment, the ridge or protrusion 20 is formed in a closed-loop form.However, no problem is encountered with disconnects in the pad trench 18due to the protrusion or ridge 20 because the conductive film 22 iscoupled to the lower-leveled conductive film through the via holes 26.

Incidentally, in the present invention, the protrusion or ridge forreducing the actual opening area of the pad trench may be provided inplurality in the pad trench or employed one in number.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

1. A damascene interconnection comprising: an interconnection trenchformed in an insulating film and a pad trench communicating therewith; aprotrusion formed by a portion not removed of said insulating film insaid pad trench to decrease a substantial opening area of said padtrench; a conductive film buried in said interconnection trench and saidpad trench; and a further conductive film; wherein the protrusion isformed as a plurality of insulating protrusions within the pad trench,the plurality of insulating protrusions reducing the overall volume ofthe conductive film of the pad trench and increasing the electricalresistance of the conductive film of the pad trench, the furtherconductive film being formed below the insulating film and the pluralityof insulating protrusions; and wherein the damascene interconnectionfurther includes a plurality of contact holes formed within the padtrench, each contact hole of the plurality of contact holes beingpositioned near at least one insulating protrusion of the plurality ofinsulating protrusions, at least some of the contact holes beingsituated between adjacent insulating protrusions, each contact hole ofthe plurality of contact holes being electrically connected between theconductive film of the pad trench and the further conductive film formedbelow the insulating film to define an electrical connection, theelectrical connection between the conductive film of the pad trench andthe further conductive film formed below the insulating film increasingthe effective volume of the conductive film of the pad trench, therebydecreasing the overall electrical resistance of the conductive film ofthe pad trench.
 2. A semiconductor device, comprising: a semiconductorsubstrate; an insulating film formed on said semiconductor substrate; aninterconnection trench formed on said insulating film and communicatingwith a semiconductor element; a pad trench formed on said insulatingfilm and communicating with said interconnection trench; a protrusionformed by a portion not removed of said insulating film in said padtrench and reducing a substantial opening area of said pad trench; aconductive film buried in said interconnection trench and said padtrench; and a further conductive film formed below said insulating film;wherein the protrusion is formed as a plurality of insulatingprotrusions within the pad trench, the plurality of insulatingprotrusions reducing the overall volume of the conductive film of thepad trench and increasing the electrical resistance of the conductivefilm of the pad trench, the further conductive film being formed belowthe insulating film and the plurality of insulating protrusions; andwherein the semiconductor device further includes a plurality of contactholes formed within the pad trench, each contact hole of the pluralityof contact holes being positioned near at least one insulatingprotrusion of the plurality of insulating protrusions, at least some ofthe contact holes being situated between adjacent insulatingprotrusions, each contact hole of the plurality of contact holes beingelectrically connected between the conductive film of the pad trench andthe further conductive film formed below the insulating film to definean electrical connection, the electrical connection between theconductive film of the pad trench and the further conductive film formedbelow the insulating film increasing the effective volume of theconductive film of the pad trench, thereby decreasing the overallelectrical resistance of the conductive film of the pad trench.